Package Layout Engineer
Celestial AI
About Celestial AI
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
ABOUT THE ROLE
We are seeking an experienced Package Layout Engineer with expertise in heterogeneous integration. The ideal candidate will have a strong background in semiconductor packaging design to drive Celestial AI’s Photonic Fabric Package solutions. This role requires cross-functional design collaboration with multiple engineering groups, such as Packaging, ASIC, AMS, Photonics, and external partners to ensure design for manufacturing, assembly, reliability, and cost.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- Package Design:
- Support layout studies for package design feasibility at Silicon/organic interposer and substrate level for multi-chip SiP packaging.
- Support package pinmap and test collateral release for test vehicle and product designs.
- Package Layout Expertise:
- Support all aspects of package layout based on I/O, SI-PI and form factor requirements, including routing, design for reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing.
- Support cross-functional package layout needs.
- 2.5D and 3D Package Design Planning and Execution:
- Support Silicon interposer and RDL based design layout solutions for advanced packaging architectures.
- Netlist management for heterogeneous chiplet assemblies using latest EDA solutions.
- Substrate Manufacturing and OSAT Assembly Engagement:
- Support activities related to substrate manufacturing such as vendor review and tape-out through various substrate suppliers and OSATs.
- Actively support test vehicle definition and design for assembly test vehicles.
QUALIFICATIONS
- Education: BS in EE/ECE/MSE/ME/ChemE or related disciplines.
- Experience: minimum 4 years of experience in Semiconductor Packaging Design of heterogeneous architectures, including silicon interposer and RDL designs.
- Technical Expertise:
- Experience working with advanced packaging design tools such as Cadence APD.
- Familiarity with AutoCAD tools and file formats.
- Layout experience for various 2.5D/3D packaging technologies including InFO, CoWoS, FoCoS and EMIB.
- Familiarity with cross-functional packaging areas: Si floor plan, package, board layout and architecture, design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, assembly, reliability, and cost.
- Familiarity with photonics packaging is a plus but not necessary.
- Substrate Vendor and OSAT Engagement:
- Experience working with substrate vendors to meet design for manufacturing, yield, and reliability.
- Experience working with OSATs to meet assembly requirements.
- Industry Knowledge: Familiarity with High Speed Signaling best practices, Signal and Power integrity requirements.
- Soft Skills: Strong analytical, problem-solving, cross-functional collaboration, project management, and technical presentation skills.
PREFERRED QUALIFICATIONS
- Experience in heterogeneous integration, fan-out packaging, chiplet architectures – co-design, layout, and netlist management.
- Familiarity of Signal and Power Integrity.
- Experience in substrate vendor and OSAT assembly engagement to meet manufacturing and assembly requirements.
LOCATION: Santa Clara, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $165,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
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